The following Modelica code corresponds to Figure 22. It has a model Spring, with two components u and y of type Real and of direction respectively in and out.

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SysPhS-1.1: p.30: 10.7.4 Modelica modeling, signal flow: Example Modelica code for Spring corresponding to 'Figure 22: Ports for signal flow in SysML' is invalid [should probably be 'input Real u;' and 'output Real y;' not 'in ...' and 'out ...']
Figure 22: Ports for signal flow in SysML
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The following Modelica code corresponds to Figure 22. It has a model Spring, with two components u and y of type Real and of direction respectively in and out.
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