Figure 29: State machine in SysML

Hold onto your hat! Such a little StateMachine example, and so many little errors, warning, and gotchas. This is why Webel IT Australia does the testing for you!

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SysPhS-1.1: 'Computer has ports u and y of type RealInSignalElement [ERROR:TYPO] and RealOutSignalElement [ERROR:TYPO] from the signal flow library (see Subclause 11.2.1), respectively.'

SysPhS-1.1: p.47: 10.12.2 SysML modeling: TYPO: Incorrect spelling of RealInSignalElement (should be RealSignalInElement) and RealOutSignalElement (should be RealSignalOutElement)

SysPhS-1.1: 'The state machine has one initial pseudostate, and two states StandBy and On. The transition from the initial pseudostate to StandBy has a relative TimeEvent with an expression indicating that the transition fires 5 seconds after the initial pseudostate is entered.'

SysPhS-1.1: 'The transition from StandBy to On has a ChangeEvent with an expression indicating that the transition is triggered when u.sigsp [ERROR] is equal to 1 (this is a signal as in signal flow simulation, not as in SysML). The transition from On to StandBy has a ChangeEvent with an expression indicating that the transition is triggered when u.sigsp [ERROR] is equal to 0. When the computer is in StandBy, y.sigsp [ERROR] is set to 8, and when the computer is On, y.sigsp [ERROR] is set to 3.'

SysPhS-1.1: p.47: 10.12.2 SysML modeling: References to 'u.sigsp' and 'y.usigsp' should be 'u.rSig' and 'y.rSig'.

SysPhS-1.1: 'The following Modelica code corresponds to Figure 29.'


model Computer
  input Real u;
  output Real y;
  ComputerSM _ComputerSM;
  model ComputerSM
    Modelica.StateGraph.InitialStep state0(nIn = 0, nOut = 1);
    Modelica.StateGraph.Step StandBy(nIn = 2, nOut = 1);
    Modelica.StateGraph.Step On(nIn = 1, nOut = 1);
    Modelica.StateGraph.Transition tr0(condition = true, enableTimer = true,
                                       waitTime = 5);
    Modelica.StateGraph.Transition tr1(condition = u==1);
    Modelica.StateGraph.Transition tr2(condition = u==0);
    Real u;
    Real y;
  equation
    connect(state0.outPort[1], tr0.inPort);
    connect(tr0.outPort, StandBy.inPort[1]);
    connect(StandBy.outPort[1], tr1.inPort);
    connect(tr1.outPort, On.inPort[1]);
    connect(On.outPort[1], tr2.inPort);
    connect(tr2.outPort, StandBy.inPort[2]);
  algorithm
    if StandBy.active then
      y := 8; 
    end if;
    if On.active then
      y := 3;
    end if;
  end ComputerSM;
equation
  u = _ComputerSM.u;
  y = _ComputerSM.y;
end Computer;

The spec version of the diagram and the corresponding Modelica code has some naming errors:

SysPhS-1.1: 10.12.2 SysML modeling: p.47: Name of StateMachine in 'Figure 29: State machine in SysML' should be ComputerSM (not Computer) for consistency with the Modelica code example

SysPhS-1.1: 10.12.2 SysML modeling: p.47, p.48: References to .sig and .rsig in 'Figure 29: State machine in SysML' and Modelica code example should be .rSig

The following is tricky:

SysPhS-1.1: When RealSignalInElement or RealSignalOutElement are used to type a SysML Port, assignments to the FlowProperty 'rSig' map to the Port name (only) when mapped to Modelica.

So the change expressions map to the following (without any rSig):


Modelica.StateGraph.Transition tr1(condition = u==1);
Modelica.StateGraph.Transition tr2(condition = u==0);

And in the algorithm the assignments in the doActivity OpaqueExpressions map to:


if StandBy.active then
  y := 8;
end if;
if On.active then
  y := 3;
end if;

(prefer however 'entry' over 'doActivity', see below).

Export of block Computer to Modelica from the MagicDraw SysML Plugin or Magic Cyber-Systems Engineer ^® (Cameo Systems Modeler^®) gives:


model Computer
  Modelica.Blocks.Interfaces.RealInput u;
  Modelica.Blocks.Interfaces.RealOutput y;
  ComputerSM _ComputerSM;
  block ComputerSM
    Modelica.StateGraph.InitialStep ComputerSM_region1_pseudostate3(nIn=0,nOut=1);
    Modelica.StateGraph.Step StandBy(nIn=2,nOut=1);
    Modelica.StateGraph.Step On(nIn=1,nOut=1);
    Modelica.StateGraph.Transition ComputerSM_region1_transition0(enableTimer=true,waitTime=5,condition=true);
    Modelica.StateGraph.Transition ComputerSM_region1_transition1(condition=u==1);
    Modelica.StateGraph.Transition ComputerSM_region1_transition2(condition=u==0);
    Modelica.Blocks.Interfaces.RealInput u;
    Modelica.Blocks.Interfaces.RealOutput y;
  equation
    connect(ComputerSM_region1_pseudostate3.outPort[1], ComputerSM_region1_transition0.inPort);
    connect(ComputerSM_region1_transition0.outPort, StandBy.inPort[1]);
    connect(StandBy.outPort[1], ComputerSM_region1_transition1.inPort);
    connect(ComputerSM_region1_transition1.outPort, On.inPort[1]);
    connect(On.outPort[1], ComputerSM_region1_transition2.inPort);
    connect(ComputerSM_region1_transition2.outPort, StandBy.inPort[2]);
  algorithm
    if StandBy.active then 
      y:=8; 
    end if;
    if On.active then 
      y:=3; 
    end if;
  end ComputerSM;
equation
  u=_ComputerSM.u;
  y=_ComputerSM.y;
end Computer;

GOTCHA: MD SysML/Cameo 19SP3 vs SysPhS-1.1: Export to Modelica does not see a 'doActivity' on a State (does not write it to a Modelica algorithm), you MUST use an 'entry'!

Note also the provided samples such as Humidifier.mdzip use 'entry'. It is assumed here that the tool's approach is correct and that the examples in the spec are incorrect:

SysPhS-1.1: p.47: 10.12.2 SysML modeling: The states StandBy and On in 'Figure 29: State machine in SysML' should probably use 'entry' not 'doActivity'.

BTW It does not matter in the MagicDraw SysML Plugin or Magic Cyber-Systems Engineer ^® (Cameo Systems Modeler^®) whether you write the opaque expressions on those 'entry' examples Modelica style like y.sig:=8 (as in the spec example) or as y.sig=8, it still exports the same way.

The exported Modelica validates in Wolfram SystemModeler, but with some warnings:


[29] 19:23 Validation of model WebelSysMLvsSysPhS.Computer 
Warning: [1325:7-1325:57]No corresponding 'inner' declaration found for component .Modelica.StateGraph.Interfaces.CompositeStepState _ComputerSM.ComputerSM_region1_pseudostate3.stateGraphRoot declared as 'outer '.
  The existing 'inner' components are:
  There are no 'inner' components defined in the model in any of the parent scopes of 'outer' component's scope: Modelica.StateGraph.InitialStep$_ComputerSM$ComputerSM_region1_pseudostate3.
  Check if you have not misspelled the 'outer' component name.
  Please declare an 'inner' component with the same name in the top scope.
  Continuing flattening by only considering the 'outer' component declaration.
Warning: [1325:7-1325:57]No corresponding 'inner' declaration found for component .Modelica.StateGraph.Interfaces.CompositeStepState _ComputerSM.StandBy.stateGraphRoot declared as 'outer '.
  The existing 'inner' components are:
  There are no 'inner' components defined in the model in any of the parent scopes of 'outer' component's scope: Modelica.StateGraph.Step$_ComputerSM$StandBy.
  Check if you have not misspelled the 'outer' component name.
  Please declare an 'inner' component with the same name in the top scope.
  Continuing flattening by only considering the 'outer' component declaration.
Warning: [1325:7-1325:57]No corresponding 'inner' declaration found for component .Modelica.StateGraph.Interfaces.CompositeStepState _ComputerSM.On.stateGraphRoot declared as 'outer '.
  The existing 'inner' components are:
  There are no 'inner' components defined in the model in any of the parent scopes of 'outer' component's scope: Modelica.StateGraph.Step$_ComputerSM$On.
  Check if you have not misspelled the 'outer' component name.
  Please declare an 'inner' component with the same name in the top scope.
  Continuing flattening by only considering the 'outer' component declaration.
Warning: [13:67-13:85]In component _ComputerSM, in relation u == /*Real*/(1),  ==  on Real numbers is only allowed inside functions.
Warning: [14:67-14:85]In component _ComputerSM, in relation u == /*Real*/(0),  ==  on Real numbers is only allowed inside functions.
Warning: [1390:9-1391:7]The variable _ComputerSM.ComputerSM_region1_transition0.t_start is inferred to be discrete due to use with pre outside a when clause. It is recommended to declare the variable as discrete.
Validation of model WebelSysMLvsSysPhS.Computer completed successfully.
The model has 24 variables and 24 equations.
Among these, 1 variable is declared as 'outer'.

Up next

Figure 30: Elements for signal flow

Notes

[ISSUE]{INFORMATIVE} SysPhS-1.1: 10.12.2 SysML modeling: p.47: Name of StateMachine in 'Figure 29: State machine in SysML' should be ComputerSM (not Computer) for consistency with the Modelica code example

[ISSUE]{INFORMATIVE} SysPhS-1.1: 10.12.2 SysML modeling: p.47, p.48: References to .sig and .rsig in 'Figure 29: State machine in SysML' and Modelica code example should be .rSig

[COMPLICATION, TIP, WARNING]{STRICT} GOTCHA: MD SysML/Cameo 19SP3 vs SysPhS-1.1: Export to Modelica does not see a 'doActivity' on a State (does not write it to a Modelica algorithm), you MUST use an 'entry'!

[ISSUE]{INFORMATIVE} SysPhS-1.1: p.47: 10.12.2 SysML modeling: TYPO: Incorrect spelling of RealInSignalElement (should be RealSignalInElement) and RealOutSignalElement (should be RealSignalOutElement)

[ISSUE]{INFORMATIVE} SysPhS-1.1: p.47: 10.12.2 SysML modeling: References to 'u.sigsp' and 'y.usigsp' should be 'u.rSig' and 'y.rSig'.

[TIP] SysPhS-1.1: When RealSignalInElement or RealSignalOutElement are used to type a SysML Port, assignments to the FlowProperty 'rSig' map to the Port name (only) when mapped to Modelica.

[ISSUE]{INFORMATIVE} SysPhS-1.1: p.47: 10.12.2 SysML modeling: The states StandBy and On in 'Figure 29: State machine in SysML' should probably use 'entry' not 'doActivity'.

Snippets (quotes/extracts)

[SysPhS-1.1] Computer has ports u and y of type RealInSignalElement [ERROR:TYPO] and RealOutSignalElement [ERROR:TYPO] from the signal flow library (see Subclause 11.2.1), respectively.