IBD: Figure 48: Internal structure of the signal processor

The slide shows the trail versions of the SignalProcessor Internal Block Diagram (IBD) Figure 48: Internal structure of the signal processor (but with Port labels once again optionally displayed inside the Port symbols):

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SysPhS-1.1: 'Figure 48 connects the signal processor input to an amplifier, the output of the amplifier to a high-pass filter in parallel with a low-pass filter, the outputs of the filters to a mixer, and the output of the mixer to the signal processor output.'

You should be able to see the correspondence with the original sketch:

Figure 46: Signal processor example (MOCKUP)

The IBD shows the initialValues compartments for a:Amplifier, hPF:HighPassFilter, and lPF:LowPassFilter.

Once again this tool display option has been used:

TIP: MagicDraw/Cameo: Consider showing the Port name and type label inside the Port symbol! CAVEAT: This loses the direction indicators on Ports typed by Blocks with flow properties (but is fine if ItemFlows show the direction, or for "contract ports").

The spec version of the diagram has overlapping Connectors from a to hPF and lPF, with a "phantom" fork that has no correspondence to a SysML model element. If you've been following this entire trail carefully you'll already know this is not Webel Best Practice:

Webel Best Practice: SysML/SysPhS: DO NOT use overlapping Connector lines from/to one Port (can be misunderstood as "summed" flow and/or physical node/fork/junction).

Amongst other things, it leads to SysML modelling problems such as:

SysPhS-1.1 spec version of 'Figure 48: Internal structure of the signal processor' shows an ItemFlow for Real on an overlapping Connector line section, which is impossible to interpret.

Dr Darren says:

I am not sure whether "bang on about" is considered an impolite expression. If you are new to SysML, or attending one of the Webel courses, or studying the Webel Best Practice modelling recommendations, I really don't want you to mimic overlapping Connector paths when working with SysML, even if you've seen it in some other diagramming tools, and even if you've seen it in a SysML or SysPhS spec sample diagram.

It's time to give the components some juice with some ConstraintBlocks as shown next .

Up next

BDD: Figure 51: Signal processing system constraint blocks

Notes

[CAPABILITY, FEATURE, STYLE, TIP] TIP: MagicDraw/Cameo: Consider showing the Port name and type label inside the Port symbol! CAVEAT: This loses the direction indicators on Ports typed by Blocks with flow properties (but is fine if ItemFlows show the direction, or for "contract ports").

[ANTI-PATTERN, MODELLING, STYLE]{STRONG} Webel Best Practice: SysML/SysPhS: DO NOT use overlapping Connector lines from/to one Port (can be misunderstood as "summed" flow and/or physical node/fork/junction).

[ANTI-PATTERN, WARNING]{STRONG} Webel vs SysPhS-1.1: Diagramming style: DO NOT recommend overlapping Connectors with "phantom" fork (or junction) as shown in in 'Figure 48: Internal structure of the signal processor'

[ISSUE] SysPhS-1.1 spec version of 'Figure 48: Internal structure of the signal processor' shows an ItemFlow for Real on an overlapping Connector line section, which is impossible to interpret.

Snippets (quotes/extracts)

[SysPhS-1.1] Figure 47 and Figure 48 show the internal structure of blocks TestBed and SignalProcessor, respectively

[SysPhS-1.1] Part properties, typed by blocks ... represent the components of the system. They are connected through ports .. which represent signal outputs and inputs ...

[SysPhS-1.1] Signals pass through ports in the direction shown by the arrows. Item flows on connectors indicate that the signals are real numbers.