Icon class icon_class fas fa-quote-left icon_class_computed fas fa-quote-left Related content BDD: Figure 49: Total system (source to sink) blocks, ports, & component properties Source SysPhS-1.1 Copyright information About Object Management Group copyright in text extracts quoted from OMG specifications for educational purposes Snippet kind INFO SysPhS Keywords RealSignalInElement Keywords SysPhS signal processing Previous snippet Figure 49-Figure 50 show block definitions for components of TestBed and SignalProcessor in Figure 47 and Figure 48, respectively. Full quote The output for SignalSource is named y and is typed by RealSignalOutElement, from the signal flow library (see Subclause 11.2.1). Next snippet The input for SignalSink is named u and is typed by RealSignalInElement, also from the library. The signal processor has an input and output, transforming the signal from the source and passing it to the sink. Related snippets A.3.2 System being modeled The signal processor and its testbed have a wave generator, an amplifier, high-pass and low-pass frequency filters, a mixer, and a signal sink, see Figure 46. Figure 47 and Figure 48 show the internal structure of blocks TestBed and SignalProcessor, respectively Part properties, typed by blocks ... represent the components of the system. They are connected through ports .. which represent signal outputs and inputs ... Signals pass through ports in the direction shown by the arrows. Item flows on connectors indicate that the signals are real numbers. Figure 47 connects a signal source to a signal processor, which it connects to a signal sink that displays the output. Figure 48 connects the signal processor input to an amplifier, the output of the amplifier to a high-pass filter in parallel with a low-pass filter, the outputs of the filters to a mixer, and the output of the mixer to the signal processor output. SysML initial values specify property values for components used in internal block diagrams. SysML initial values specify property values for components used in internal block diagrams. Figure 49-Figure 50 show block definitions for components of TestBed and SignalProcessor in Figure 47 and Figure 48, respectively. Related snippets (backlinks) The input for SignalSink is named u and is typed by RealSignalInElement, also from the library. The signal processor has an input and output, transforming the signal from the source and passing it to the sink. In Figure 50, amplifiers, low-pass filters, and high-pass filters, each have an input and an output. Since they are similar in this sense, a generalized TwoPinSignalComponent component has an input u and an output y. Mixers have inputs u1 and u2, and an output y. Signal flow is the movement of numbers between system components. These numbers might reflect physical quantities or not. In this example, they do not ... Each kind of component has its own behaviors, defined as constraints ... Signals flowing in and out of components are modeled by ports typed by interface blocks that have flow properties typed by numbers. In this example, ports are typed by RealSignalOutElement and RealSignalInElement from the signal flow library ... which both have a flow property rSig typed by Real, from SysML, as shown in Figure 49. This value type has no unit, reflecting that the signals are not measurements of physical quantities and do not follow conservation laws. The amplifier, filters (high-pass and low-pass), signal source, and signal sink have properties g, alpha and xi, amp, and scope, respectively. The amp, alpha and g properties have the PhSConstant stereotype applied, specifying that their values are constant during each simulation run. The xi and scope properties have the PhSVariable stereotype applied, specifying that their values might vary during simulation. Equations define mathematical relationships between the values of numeric variables. Equations in SysML, are constraints in constraint blocks that use properties of the blocks (parameters) as variables. In this example, a constraint block BinarySignalComponentConstraint defines the parameters for one input (ip) and one output (op), common to amplifiers, low-pass filters, and high-pass filters, as shown in Figure 51. The amplifier, low-pass fil[t]er, and high-pass filter constraints show the input-output relationship of these components as the signal passes through them. The amplifier changes the signal strength by a factor gain, the low-pass filter eliminates the high-frequency components of the incoming signal, and the high-pass filter eliminates the low-frequency components of the signal. The mixer constraint specifies the relationship between its one output and the two inputs that come from the low-pass and high-pass filters. The constraint defines the output to be the average of the inputs. The source constraint specifies a sine wave signal with the parameter amp as its amplitude. The sink constraint displays (scopes) the output signal from the signal processor. Equations in constraint blocks are applied to components using binding connectors in component parametric diagrams. Component parametric diagrams show properties typed by constraint blocks (constraint properties), as well as component and port simulation variables and constants. Binding connectors link constraint parameters to simulation variables and constants, indicating their values must be the same. Figure 52 through Figure 57 show parametric diagrams for the source, amplifier, high-pass fil[t]er, low-pass filter, mixer, and sink, respectively. Visit also Visit also (backlinks) Flags
